Very large scale integrated (VLSI) circuit chips are conventionally formed on a single wafer of silicon which is then scribed to facilitate breaking out of individual chips for separate packaging. Since the packaging of an individual chip adds significantly to its manufacturing cost, it is desirable to fully test the individual chips while they are still an integral part of the wafer to avoid the expense of packaging a defective chip. There are several types of tests commonly performed on the individual chips including generally, functional tests for proper circuit operation, electrical parameter tests for correct input and output signal characteristics, and delay tests for circuit operations at the requisite speeds.
Testing chips when they are part of the wafer requires a method for getting signals into, and reading signals from, the chip's input/output (I/O) pads. Probe mechanisms have been developed to satisfy this need. A probe is a mechanical arm, electriclly conductive, with a fine point on one end to make electrical contact with an I/O pad; the other end of the probe being wired to electronic testers. Probe systems have been fabricated that have as many probes as the number of I/O pads on the chip being tested. The contact ends of the probes are arranged in the same pattern as the I/O pads such that when the chip is aligned under the probes, an electrical signal from the tester causes the probe points to lower and make contact with the I/O pads.
When contact is made with all the I/O pads, test patterns can be applied to the input pads and a clock signal, if necessary, is generated by the tester and sent to the appropriate input pad. The response of the circuitry on the chip to the input signals can then be read by the tester through the probes connected to the output pads. The tester can compare the output pattern read from the chip to the pattern that is expected, based upon the input pattern, and determine if the chip is functioning correctly. Such probe systems thus perform the functional test requirement of testing chips while still part of the wafer.
Such probe systems are also used for delay measurements by the use of special test chips. These test chips are placed at strategic locations relative to the array of desired functional chips, thereby using up space on the wafer that could otherwise be used for additional functional chips. The test chips have a small number of I/O pads and the delay test is performed using a probe mechanism that is different from that used for functional tests of the other chips. Because of the small number of I/O pads on the test chip, the probe arms on the delay tester can be made very small. Therefore, the inductance of the probe arms does not affect the delay test results. Since each test chip displaces a potentially usable functional chip, only a small number of test chips are used on each wafer.
If an entire wafer is not rejected based upon the results of the delay testing of the special chips on the wafer, then all the functional chips that passed functional tests must still be delay tested after being individually packaged.
Performing delay tests on a normal chip in VLSI technology has not heretofore been practical for two major reasons: (1) circuit delays decreased; and (2) the number of I/O pads increased as VLSI technology developed.
The decrease in circuit delays mean that the time between the application of the input pulses and the detection of the output pulse becomes smaller, dictating a more precise measurement of the time involved if the answers are to be meaningful. As the circuit density of the chip and the number of I/O pads increased, the size of the chip did not increase in the same proportion. In fact, as the number of I/O pads on a chip increased, they had to be made smaller and closer together.
The end of the probe arm which is wired to the tester is much wider than the contact end. Therefore, the row of probe arms along each side of a chip form a "fan", narrow at the probe end and wide at the end wired to the tester. Since a chip is typically square, with I/O pads and probe arms along each side, as the number of I/O pads increased, the length of the probe arm has to increase because the four "fans" get wider at the tester end of the probe arm. This increased probe length adds significant inductance to the test circuits used for delay testing.
The rise and fall times of the signals generated and measured must be small compared to the delay being measured. Further, the switching point of the output signal, with respect to the switching point of the input signal, must be measured more accurately. However, the inductance of the longer probe distorts the signals used for the delay test, lengthening the otherwise fast rise or fall times. Thus, even though a delay can be measured, the time between the switchings of the first input circuit and last output circuit can not be determined with enough accuracy to make a go/no-go decision.
Recent advances in VLSI technology have included integral test circuitry consisting of a shift register around the periphery of the chip. The shift register has a stage, or storage location, physically corresponding to each of the I/O pads of the chip. The shift register is normally used by the tester to functionally test the chip. Schemes of this type are disclosed in the literature (see, for example, U.S. Pat. Nos. 4,495,628 and 4,495,629 and 4,587,480).
In these known testing schemes, additional circuitry is used to gate a signal from the output of the shift register, with one inversion, back into the shift register. All stages of the shift register are held open so that the signal repeatedly passes through the shift register and can be monitored on the output. When the shift register is used in this manner, it is called a ring oscillator. Each stage of the ring oscillator causes a double inversion of the signal so the signal that appears at the output, because of the single inversion of the additional circuitry, is the inversion of what the tester originally sent. The additional circuitry gates this output signal back to the tester for detection, as well as to the inverter to circulate through the ring oscillator again. The transit time of the signal through all the stages of the ring oscillator is a measure of the delay of the circuits on the chip.
If conventional testing methods are used, the cost of testing an integrated circuit chip will increase exponentially as the complexity of the chip increases. In the ASIC (Application Specific Integrated Circuit) market, VLSI chips can be fabricated with several tens of thousands of logic gates. These chips are typically manufactured in small quantities (10 to 1000) compared to large quantities (one million) for a custom chip. In small manufacturing quantities, the cost of generating the test patterns can be greater than the deisgn and fabrication cost for the chip.
Individual VLSI chips which successfully pass testing while still integrally a part of the wafer are then scribed and broken free for individual packaging and re-testing and subsequent assembly and connection with other components into more comprehensive circuits, usually on printed circuit (PC) boards. A PC board may contain more than one hundred of these chips and more than ten thousand interconnecting wires. A PC board of this complexity can not be assembled without errors. Therefore a test of this PC board must not only detect errors, it must collect enough information to determine the cause of the error and the repair procedure. The cost of generating a test pattern and testing such a PC board can be prohibitively high if conventional test methods are used.
Adding logic gates to a VLSI chip to improve the testability is a practical and economical method of solving the testing problem at the chip level, at the PC board level, and at the system level. It is well known in the state of the art that scan logic in a chip can divide a chip into islands of combinational logic such that computer algorithms can be used to automatically generate high quality test patterns at very low cost. However even with scan logic, the cost is very high for generating adeqzuate test patterns and fault repair procedures for complex PC boards. It is frequently desirable to perform substantially the same circuit tests on individual VLSI circuit chips at each stage of fabrication, manufacturing and assembly to develop comp rative data that can characterize defects or unacceptable production practices which destroy circuits or denigrate circuit performance. It is desirable to electrically isolate the chip from the PC board for certain test procedures.
This electrical isolation from the PC board would allow the chip input pads to be driven from the scan ring and the chip output pads to be measured by the scan ring without regard to the logic state of the other chips on the board. In this manner chip testing at the board level could be done with the same test pattern that was used at wafer probe.
The scan rings could also be used to drive the output pads on one chip while measuring the input pads on other chips on the PC board and thus test the board wiring interconnections. If the internal logic of the chip was electrically isolated from the PC board, the chip would not have to be considered when testing the board wiring. The PC board interconnection test patterns could be automatically generated from the PC board wiring list, and since each pad of each VLSI chip on the PC board could be either driven or measured, PC board wiring and assembly errors could be isolated so that repair procedures could easily be generated.